/* RS232 test 1: by Antti Karttunen, 30. 9. 2007.
   Test of a UART transmitter module, borrowed from
   http://www.opencores.org/cores/uart16550/
 */

module rstest1(input CLK,
               input RST,
               input PB_IN0,
               input PB_IN1,
               input [7:0] SW_IN, // For setting the baud rate.
               output TXD,
               output [7:0] LED_OUT
              );

reg [7:0] outbyte = 8'b01011010; // ascii 90. (octal 132) = 'Z'.

wire [11:0] dl = {4'b0000,SW_IN[7:0]};

reg [11:0] dlc = 12'b000000000000;

reg enable_for_uart;
wire tf_push = PB_IN0;
wire tf_reset = PB_IN1;


// We set UART_LC_DL, UART_LC_BC, UART_LC_SP, UART_LC_EP, UART_LC_PE and UART_LC_SB as zeros.
// We use 8 data bits, no parity, one stop bit. (8N1).
parameter UART_LCR_8N1 = 8'b00000011;

uart_transmitter RS232SEND(.clk(CLK),
                           .wb_rst_i(RST),
                           .lcr(UART_LCR_8N1),
                           .tf_push(tf_push),
                           .wb_dat_i(outbyte),
                           .enable(enable_for_uart),
                           .stx_pad_o(TXD),
                           .tstate(LED_OUT[7:5]),   // This is an output signal.
                           .tf_count(LED_OUT[4:0]), // As well.
                           .tx_reset(tf_reset),
                           .lsr_mask(tf_reset)
                          );



// Frequency divider
always @(posedge CLK or posedge RST) 
begin
	if (RST)
//		dlc <= #1 0;
                dlc <= dl - 1; // AK's addition.
	else
// WAS:		if (start_dlc | ~ (|dlc))
		if (~(|dlc))
  			dlc <= #1 dl - 1;               // preset counter
		else
			dlc <= #1 dlc - 1;              // decrement counter
end

// Enable signal generation logic
always @(posedge CLK or posedge RST)
begin
	if (RST)
		enable_for_uart <= #1 1'b0;
	else
		if (|dl & ~(|dlc))     // dl>0 & dlc==0
			enable_for_uart <= #1 1'b1;
		else
			enable_for_uart <= #1 1'b0;
end

endmodule