/* RS232 test 1: by Antti Karttunen, 30. 9. 2007.
   Test of a UART transmitter module, borrowed from
   http://www.opencores.org/cores/uart16550/
 */

module rstest1(input CLK,
               input RST,
               input PB_IN0,
               input PB_IN1,
               input [7:0] SW_IN, // For setting the baud rate.
               output TXD,
               output [7:0] LED_OUT
              );

wire PBD_IN0;
reg pbd_in0_prev = 0; // is saved here also.
wire pb1_pressed = (PBD_IN0 & ~pbd_in0_prev);

debounced_button DBB1(CLK,PB_IN0,PBD_IN0);

reg [4:0] outchar5lsb = 5'b00000; // Ranges from 00000 to 11111.
wire [7:0] outchar = {3'b010,outchar5lsb}; // From ascii 64. ('@') to 95 ('_').

parameter out_cr = 8'b00001101; // Ascii 0D.
parameter out_lf = 8'b00001010; // Ascii 0A.

parameter ts_send_other = 2'b00;
parameter ts_send_cr = 2'b01;
parameter ts_send_lf = 2'b11;

reg [1:0] top_state = 2'b00;

wire [7:0] outbyte = ((ts_send_cr==top_state) ? out_cr : ((ts_send_lf==top_state) ? out_lf : outchar));

wire send_byte_to_fifo = (pb1_pressed | top_state[0]);

wire [11:0] dl = {4'b0000,SW_IN[7:0]};

reg [11:0] dlc = 12'b000000000000;

reg enable_for_uart;
// reg tf_push = 1'b0;
wire tf_reset = PB_IN1;

wire [2:0] tstate;
assign LED_OUT[7:5] = tstate;

parameter s_send_stop   = 3'd4;

// We set UART_LC_DL, UART_LC_BC, UART_LC_SP, UART_LC_EP, UART_LC_PE and UART_LC_SB as zeros.
// We use 8 data bits, no parity, one stop bit. (8N1).
parameter UART_LCR_8N1 = 8'b00000011;

uart_transmitter RS232SEND(.clk(CLK),
                           .wb_rst_i(RST),
                           .lcr(UART_LCR_8N1),
                           .tf_push(send_byte_to_fifo),
                           .wb_dat_i(outbyte),
                           .enable(enable_for_uart),
                           .stx_pad_o(TXD),
                           .tstate(tstate),   // This is an output signal.
                           .tf_count(LED_OUT[4:0]), // As well.
                           .tx_reset(tf_reset),
                           .lsr_mask(tf_reset)
                          );




// Push button 1:
always @(posedge CLK or posedge RST) 
begin
        pbd_in0_prev  <= PBD_IN0;
        if (RST)
		pbd_in0_prev  <= 0;
	else if(pb1_pressed)
                outchar5lsb <= outchar5lsb + 1;

end

always @(posedge CLK or posedge RST) 
begin
        if (RST)
	    top_state  <= ts_send_other;
	else
            case (top_state)
		ts_send_other : top_state <= (pb1_pressed ? ts_send_cr : ts_send_other);
		ts_send_cr : top_state <= ts_send_lf;
		ts_send_lf : top_state <= ts_send_other;
		default : top_state <= ts_send_other;
            endcase
end


// Frequency divider
always @(posedge CLK or posedge RST) 
begin
        if (RST)
//		dlc <= #1 0;
                dlc <= dl - 1; // AK's addition.
	else
// WAS:		if (start_dlc | ~ (|dlc))
		if (~(|dlc))
  			dlc <= #1 dl - 1;               // preset counter
		else
			dlc <= #1 dlc - 1;              // decrement counter
end

// Enable signal generation logic
always @(posedge CLK or posedge RST)
begin
	if (RST)
		enable_for_uart <= #1 1'b0;
	else
		if (|dl & ~(|dlc))     // dl>0 & dlc==0
			enable_for_uart <= #1 1'b1;
		else
			enable_for_uart <= #1 1'b0;
end

endmodule