/* RS232 test 1: by Antti Karttunen, 30. 9. 2007.
   Test of a UART transmitter module, borrowed from
   http://www.opencores.org/cores/uart16550/

   This version, miditest1.v Mar 23 2010,
   uses the inverted version of the transmitter
   and outputs to our MIDIOUT pin.
 */

module miditest1(input CLK,
                 input RST,
                 input PB_IN0,
                 output MIDIOUT,
                 output [7:0] LED_OUT
                );

wire PBD_IN0;
reg pbd_in0_prev = 0; // is saved here also.
wire pb1_pressed = (PBD_IN0 & ~pbd_in0_prev);

debounced_button DBB1(CLK,PB_IN0,PBD_IN0);

reg [4:0] midinote5lsb = 5'b00000; // Ranges from 00000 to 11111.
wire [7:0] midinote = {3'b010,midinote5lsb}; // From decimal 64 to 95. (64+31)

assign LED_OUT[7:0] = midinote; // Just for debugging

parameter ts_waiting1      = 2'b00;
parameter ts_send_note_on  = 2'b01;
parameter ts_waiting2      = 2'b11;
parameter ts_send_note_off = 2'b10;

reg [1:0] top_state = ts_waiting1;

wire [7:0] velocity = ((ts_waiting1==top_state) ? 8'h7F : 8'h00);
wire sendthem = (top_state[0]^top_state[1]); // Raise sendthem signal only with states ts_send_note_on or ts_send_note_off

midiout3bytes MIDINoteOnOff(.CLK(CLK),
                            .RST(RST),
                            .byte1(8'h90),
                            .byte2(midinote),
                            .byte3(velocity),
                            .sendthem(sendthem),
                            .MIDIOUT(MIDIOUT)
                           );



always @(posedge CLK or posedge RST) 
begin
        pbd_in0_prev  <= PBD_IN0;
        if(RST)
           begin
            pbd_in0_prev  <= 0;
	    top_state  <= ts_waiting1;
           end
	else
           case (top_state)

		ts_waiting1        : top_state <= (pb1_pressed ? ts_send_note_on : ts_waiting1);
		ts_send_note_on    : top_state <= ts_waiting2;

		ts_waiting2        : top_state <= (pb1_pressed ? ts_send_note_off : ts_waiting2);
		ts_send_note_off   : 
                 begin
                  midinote5lsb <= midinote5lsb + 1; top_state <= ts_waiting1;
                 end

           endcase
end

endmodule