/* RS232 test 1: by Antti Karttunen, 30. 9. 2007.
   Test of a UART transmitter module, borrowed from
   http://www.opencores.org/cores/uart16550/

   This version, miditest1.v Mar 23 2010,
   uses the inverted version ofthe transmitter
   and outputs to our MIDIOUT pin.
 */

module miditest1(input CLK,
               input RST,
               input PB_IN0,
               input PB_IN1,
               input [7:0] SW_IN, // For setting the baud rate.
               output MIDIOUT,
               output [7:0] LED_OUT
              );

wire PBD_IN0;
reg pbd_in0_prev = 0; // is saved here also.
wire pb1_pressed = (PBD_IN0 & ~pbd_in0_prev);

debounced_button DBB1(CLK,PB_IN0,PBD_IN0);

reg [4:0] outchar5lsb = 5'b00000; // Ranges from 00000 to 11111.
wire [7:0] outchar = {3'b010,outchar5lsb}; // From decimal 64 to 95. (64+31)

parameter out_cr = 8'b00001101; // Ascii 0D.
parameter out_lf = 8'b00001010; // Ascii 0A.

parameter out_00 = 8'b00000000; // Byte 0x00, velocity off.
parameter out_90 = 8'b10010000; // Byte 0x90, NoteOn.
parameter out_7F = 8'b01111111; // Byte 0x7F, maximum velocity. (loudness).

parameter ts_waiting1     = 3'b000;
parameter ts_send_90a     = 3'b001;
parameter ts_send_note_a  = 3'b011;
parameter ts_send_7F      = 3'b010;
parameter ts_waiting2     = 3'b100;
parameter ts_send_90b     = 3'b101;
parameter ts_send_note_b  = 3'b111;
parameter ts_send_00      = 3'b110;

reg [2:0] top_state = ts_waiting1;

wire [7:0] outbyte = ((2'b01==(top_state&(3'b011))) ? out_90 : ((2'b11==(top_state&(3'b011))) ? outchar : ((ts_send_7F==top_state) ? out_7F : out_00)));

wire send_byte_to_fifo = (top_state[0]|top_state[1]); // if top_state is neither ts_waiting1 nor ts_waiting2

wire [11:0] dl = {4'b0000,SW_IN[7:0]};

reg [11:0] dlc = 12'b000000000000;

reg enable_for_uart;
// reg tf_push = 1'b0;
wire tf_reset = PB_IN1;

wire [2:0] tstate;
assign LED_OUT[7:5] = tstate;

parameter s_send_stop   = 3'd4;

// From http://en.wikipedia.org/wiki/MIDI_1.0

// It consists physically of a one-way (simplex) digital
// current loop serial communications electrical connection
// signaling at 31,250 bits per second.
// 8-N-1 format, i.e. one start bit (must be 0), eight data bits,
// no parity bit and one stop bit (must be 1), is used.


// We set UART_LC_DL, UART_LC_BC, UART_LC_SP, UART_LC_EP, UART_LC_PE and UART_LC_SB as zeros.
// We use 8 data bits, no parity, one stop bit. (8N1).
parameter UART_LCR_8N1 = 8'b00000011;

uart_transmitter_inverted MIDISEND(.clk(CLK),
                           .wb_rst_i(RST),
                           .lcr(UART_LCR_8N1),
                           .tf_push(send_byte_to_fifo),
                           .wb_dat_i(outbyte),
                           .enable(enable_for_uart),
                           .stx_pad_o(MIDIOUT),
                           .tstate(tstate),   // This is an output signal.
                           .tf_count(LED_OUT[4:0]), // As well.
                           .tx_reset(tf_reset),
                           .lsr_mask(tf_reset)
                          );




// Push button 1:
always @(posedge CLK or posedge RST) 
begin
        pbd_in0_prev  <= PBD_IN0;
        if (RST)
		pbd_in0_prev  <= 0;
	else if(ts_send_00 == top_state)
                outchar5lsb <= outchar5lsb + 1;

end

always @(posedge CLK or posedge RST) 
begin
        if (RST)
	    top_state  <= ts_waiting1;
	else
            case (top_state)

		ts_waiting1    : top_state <= (pb1_pressed ? ts_send_90a : ts_waiting1);
		ts_send_90a    : top_state <= ts_send_note_a;
		ts_send_note_a : top_state <= ts_send_7F;
		ts_send_7F     : top_state <= ts_waiting2;

		ts_waiting2    : top_state <= (pb1_pressed ? ts_send_90b : ts_waiting2);
		ts_send_90b    : top_state <= ts_send_note_b;
		ts_send_note_b : top_state <= ts_send_00;
		ts_send_00     : top_state <= ts_waiting1;

           endcase
end


// Frequency divider
always @(posedge CLK or posedge RST) 
begin
        if (RST)
//		dlc <= #1 0;
                dlc <= dl - 1; // AK's addition.
	else
// WAS:		if (start_dlc | ~ (|dlc))
		if (~(|dlc))
  			dlc <= #1 dl - 1;               // preset counter
		else
			dlc <= #1 dlc - 1;              // decrement counter
end

// Enable signal generation logic
always @(posedge CLK or posedge RST)
begin
	if (RST)
		enable_for_uart <= #1 1'b0;
	else
		if (|dl & ~(|dlc))     // dl>0 & dlc==0
			enable_for_uart <= #1 1'b1;
		else
			enable_for_uart <= #1 1'b0;
end

endmodule