life1 Project Status (01/29/2010 - 21:32:41)
Project File:	life1.ise	Implementation State:	Programming File Generated
Module Name:	life1	Errors:	No Errors
Target Device:	xc3s200-4ft256	Warnings:	24 Warnings (0 new)
Product Version:	ISE 11.1	Routing Results:	All Signals Completely Routed
Design Goal:	Balanced	Timing Constraints:	All Constraints Met
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:	0 (Setup: 0, Hold: 0, Component Switching Limit: 0) (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	376	3,840	9%
Number of 4 input LUTs	1,160	3,840	30%
Number of occupied Slices	753	1,920	39%
Number of Slices containing only related logic	753	753	100%
Number of Slices containing unrelated logic	0	753	0%
Total Number of 4 input LUTs	1,224	3,840	31%
Number used as logic	1,158
Number used as a route-thru	64
Number used as Shift registers	2
Number of bonded IOBs	57	173	32%
Number of BUFGMUXs	1	8	12%
Average Fanout of Non-Clock Nets	3.40

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0, Component Switching Limit: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Fri Jan 29 21:29:57 2010	0	12 Warnings (0 new)	4 Infos (0 new)
Translation Report	Current	Fri Jan 29 21:30:12 2010	0	0	0
Map Report	Current	Fri Jan 29 21:30:33 2010	0	6 Warnings (0 new)	3 Infos (0 new)
Place and Route Report	Current	Fri Jan 29 21:31:08 2010	0	6 Warnings (0 new)	0
Power Report
Post-PAR Static Timing Report	Current	Fri Jan 29 21:31:17 2010	0	0	2 Infos (0 new)
Bitgen Report	Current	Fri Jan 29 21:32:39 2010	0	4 Warnings (0 new)	1 Info (0 new)

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 01/29/2010 - 21:32:42