life1 Project Status (01/29/2010 - 21:32:41)
Project File: life1.ise Implementation State: Programming File Generated
Module Name: life1
  • Errors:
No Errors
Target Device: xc3s200-4ft256
  • Warnings:
24 Warnings (0 new)
Product Version:ISE 11.1
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0, Component Switching Limit: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 376 3,840 9%  
Number of 4 input LUTs 1,160 3,840 30%  
Number of occupied Slices 753 1,920 39%  
    Number of Slices containing only related logic 753 753 100%  
    Number of Slices containing unrelated logic 0 753 0%  
Total Number of 4 input LUTs 1,224 3,840 31%  
    Number used as logic 1,158      
    Number used as a route-thru 64      
    Number used as Shift registers 2      
Number of bonded IOBs 57 173 32%  
Number of BUFGMUXs 1 8 12%  
Average Fanout of Non-Clock Nets 3.40      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Jan 29 21:29:57 2010012 Warnings (0 new)4 Infos (0 new)
Translation ReportCurrentFri Jan 29 21:30:12 2010000
Map ReportCurrentFri Jan 29 21:30:33 201006 Warnings (0 new)3 Infos (0 new)
Place and Route ReportCurrentFri Jan 29 21:31:08 201006 Warnings (0 new)0
Power Report     
Post-PAR Static Timing ReportCurrentFri Jan 29 21:31:17 2010002 Infos (0 new)
Bitgen ReportCurrentFri Jan 29 21:32:39 201004 Warnings (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 01/29/2010 - 21:32:42