Design Overview for life1

PropertyValue
Project Name:c:\karttu\fpga\esimes\lauta8x8
Target Device:xc3s200
Report Generated:Wednesday 08/24/05 at 19:14
Printable Summary (View as HTML)life1_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops:2803,8407% 
Number of 4 input LUTs:9633,84025% 
Logic Distribution:    
Number of occupied Slices:6741,92035% 
Number of Slices containing only related logic:674674100% 
Number of Slices containing unrelated logic:06740% 
Total Number 4 input LUTs:1,0003,84026% 
Number used as logic:963   
Number used as a route-thru:37   
Number of bonded IOBs:4517326% 
Number of GCLKs:1812% 

Performance Summary

PropertyValue
Final Timing Score:0
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:0

Failing Constraints

Constraint(s)RequestedActualLogic Levels
All Constraints Met   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentWednesday 08/24/05 at 19:13
Translation ReportCurrentWednesday 08/24/05 at 19:13
Map ReportCurrentWednesday 08/24/05 at 19:13
Pad ReportCurrentWednesday 08/24/05 at 19:14
Place and Route ReportCurrentWednesday 08/24/05 at 19:14
Post Place and Route Static Timing ReportCurrentWednesday 08/24/05 at 19:14
Bitgen ReportCurrentWednesday 08/24/05 at 19:14