/* lauta6 - Test for Mefisto Board through User Extension Port and Interface. */

module lauta6(CLK,PB_IN,SW_IN,BCOL_IN,BCOL_OUT,BROW,LED_OUT);
input CLK;
input [3:0] PB_IN;
input [7:0] SW_IN;
input [7:0] BCOL_IN;
output [7:0] BCOL_OUT;
output [7:0] BROW;
output [7:0] LED_OUT;


// wire RST = PB_IN[3];


reg [7:0] BOARD_ROW0 = 8'b10000001;
reg [7:0] BOARD_ROW1 = 8'b10001001;
reg [7:0] BOARD_ROW2 = 8'b10010001;
reg [7:0] BOARD_ROW3 = 8'b10011001;
reg [7:0] BOARD_ROW4 = 8'b10100001;
reg [7:0] BOARD_ROW5 = 8'b10101001;
reg [7:0] BOARD_ROW6 = 8'b10110001;
reg [7:0] BOARD_ROW7 = 8'b10111001;

wire [7:0] PIECES_ROW0;
wire [7:0] PIECES_ROW1;
wire [7:0] PIECES_ROW2;
wire [7:0] PIECES_ROW3;
wire [7:0] PIECES_ROW4;
wire [7:0] PIECES_ROW5;
wire [7:0] PIECES_ROW6;
wire [7:0] PIECES_ROW7;


mefi8x8a BOARD_IO(.CLK(CLK),
                  .BCOL_IN(BCOL_IN),
                  .BCOL_OUT(BCOL_OUT),
                  .BROW(BROW),
                  .LEDS2LIT0(BOARD_ROW0),
                  .LEDS2LIT1(BOARD_ROW1),
                  .LEDS2LIT2(BOARD_ROW2),
                  .LEDS2LIT3(BOARD_ROW3),
                  .LEDS2LIT4(BOARD_ROW4),
                  .LEDS2LIT5(BOARD_ROW5),
                  .LEDS2LIT6(BOARD_ROW6),
                  .LEDS2LIT7(BOARD_ROW7),
                  .PIECES0(PIECES_ROW0),
                  .PIECES1(PIECES_ROW1),
                  .PIECES2(PIECES_ROW2),
                  .PIECES3(PIECES_ROW3),
                  .PIECES4(PIECES_ROW4),
                  .PIECES5(PIECES_ROW5),
                  .PIECES6(PIECES_ROW6),
                  .PIECES7(PIECES_ROW7)
                 );


assign LED_OUT = {PIECES_ROW0[0],PIECES_ROW0[1],PIECES_ROW0[2],PIECES_ROW0[3],PIECES_ROW0[4],PIECES_ROW0[5],PIECES_ROW0[6],PIECES_ROW0[7]};


always @(posedge CLK)
  begin
// if(RST)
//  begin
//  end
// else
    begin
      BOARD_ROW0 <= PIECES_ROW0;
      BOARD_ROW1 <= PIECES_ROW1;
      BOARD_ROW2 <= PIECES_ROW2;
      BOARD_ROW3 <= PIECES_ROW3;
      BOARD_ROW4 <= PIECES_ROW4;
      BOARD_ROW5 <= PIECES_ROW5;
      BOARD_ROW6 <= PIECES_ROW6;
      BOARD_ROW7 <= PIECES_ROW7;
    end
  end

endmodule