/* lauta1 - Test User Extension Port B1. */

module lauta1(CLK,PB_IN,SW_IN,BCOL_IN,BCOL_OUT,BROW,LED_OUT);
input CLK;
input [3:0] PB_IN;
input [7:0] SW_IN;
input [7:0] BCOL_IN;
output [7:0] BCOL_OUT;
output [7:0] BROW;
output [7:0] LED_OUT;

reg [7:0] USR1IN = 8'b0;
reg [7:0] USR1OUT = 8'b0;
reg [7:0] USR2OUT = 8'b0;

assign BCOL_OUT = USR1OUT;
assign BROW = USR2OUT;
assign LED_OUT = ~USR1IN;

always @(posedge CLK)
  begin
   USR1IN  <= {BCOL_IN[0],BCOL_IN[1],BCOL_IN[2],BCOL_IN[3],BCOL_IN[4],BCOL_IN[5],BCOL_IN[6],BCOL_IN[7]};
   USR2OUT <= {SW_IN[0],SW_IN[1],SW_IN[2],SW_IN[3],SW_IN[4],SW_IN[5],SW_IN[6],SW_IN[7]};
   USR1OUT[3:0] <= {PB_IN[0],PB_IN[1],PB_IN[2],PB_IN[3]};
   USR1OUT[7:4] <= {PB_IN[0],PB_IN[1],PB_IN[2],PB_IN[3]};
  end

endmodule