/* issi32a: by karttu, May 30 2005.
            Read/write controller for
            ISSI IS61LV25616AL Asynchronous Static RAM memory.

            Use both chips (IC10 & IC11) to obtain 2x16 = 32 bits.
 */

module issi32a(input CLK,
               output [17:0] ISSI_ADDR,
               inout [31:0] ISSI_DATA_IO,
               output ISSI_CE1N,
               output ISSI_CE2N,
               output ISSI_OEN,
               output ISSI_WEN,
               output ISSI_LB1N,
               output ISSI_LB2N,
               output ISSI_UB1N,
               output ISSI_UB2N,

               input STARTWRITE, // 1 if we are reading, 0 if writing.
               input [17:0] ADDR,
               input [31:0] DATAWRITTEN,
               output [31:0] DATAREAD,
               output WRITEREADY
              );


reg [17:0] copy_of_ADDR;
reg [31:0] copy_of_DATAWRITTEN;

parameter   low = 1'b0;
parameter  high = 1'b1;
parameter low32 = 32'b00000000000000000000000000000000;
parameter   z32 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;

// If the calling module raises STARTWRITE signal, then
// the ISSI_OEN is immediately raised (output disabled),
// and the state will be changed from the default state
// ST_READ to ST_WRITE1 (on the next cycle).
// The ADDR bus should be set to the requested write address,
// and DATAWRITTERN bus to the word to bre written,
// ALREADY at the time STARTWRITE signal was raised.
// (They are copied to registers at that time, so it
//  doesn't matter if the calling module will change
//  them during the write cycles).

parameter [1:0] ST_READ   = 2'b00;
parameter [1:0] ST_WRITE1 = 2'b01;
parameter [1:0] ST_WRITE2 = 2'b11; // In this state we take ISSI_WEN low.
parameter [1:0] ST_WRITE3 = 2'b10; // Here we take it back high and raise WRITEREADY

reg [1:0] state = ST_READ;


assign ISSI_CE1N = low;
assign ISSI_CE2N = low;
assign ISSI_OEN  = (STARTWRITE | (ST_READ != state));
assign ISSI_LB1N = low;
assign ISSI_LB2N = low;
assign ISSI_UB1N = low;
assign ISSI_UB2N = low;
assign ISSI_WEN  = ~(state[1] & state[0]); // (ST_WRITE2 != state);

assign ISSI_ADDR = ((ST_READ == state) ? ADDR : copy_of_ADDR);
assign ISSI_DATA_IO = ((ST_READ == state) ? z32 : copy_of_DATAWRITTEN);
assign DATAREAD = ((ST_READ == state) ? ISSI_DATA_IO : low32);

assign WRITEREADY = (ST_WRITE3 == state);

always @(posedge CLK)
  begin
/*
    state <= (2'b00 == state)
               ? 2'b01
               : (2'b01 == state)
                   ? 2'b11
                   : (2'b11 == state)
                       ? 2'b10: 2'b00;
 */
    case(state)
      ST_READ:
       begin
        if(STARTWRITE)
         begin
            state[0] <= ~state[0];
            copy_of_ADDR <= ADDR;
            copy_of_DATAWRITTEN <= DATAWRITTEN;
         end
       end
      ST_WRITE1:
       begin
        state[1] <= ~state[1];
       end
      ST_WRITE2:
       begin
        state[0] <= ~state[0];
       end
      ST_WRITE3:
       begin
        state[1] <= ~state[1];
       end
    endcase
  end

endmodule