/* inc4fex:  by karttu, Jan 2 2005.
             Increment the four-digit factorial expansion
             specified in one-bit register in_f0 (the least
             significant digit) and the next thee digits
             in three shift registers (in_f1 - in_f3)
             and give the results in out_fo - out_f3.
             (in f1-f3 we use "one hot" encoding).

             Note that in_f0 can be used as a kind
             of "incrementation enable" signal, because
             the incrementing is carried only when
             it is 1.
 */

module inc4fex(input in_f0,
               input [2:0] in_f1,
               input [3:0] in_f2,
               input [4:0] in_f3,
               output out_f0,
               output [2:0] out_f1,
               output [3:0] out_f2,
               output [4:0] out_f3);

assign out_f0 = ~in_f0;

genvar i;

assign out_f1[0] = (in_f0 ? in_f1[2] : in_f1[0]);
generate
 for(i=1; i<=2; i=i+1) begin : f1_loop
  assign out_f1[i] = (in_f0 ? in_f1[i-1] : in_f1[i]);
 end //end of the for loop inside the generate block
endgenerate

assign out_f2[0] = ((in_f0 && in_f1[2]) ? in_f2[3] : in_f2[0]);
generate
 for(i=1; i<=3; i=i+1) begin : f2_loop
  assign out_f2[i] = ((in_f0 && in_f1[2]) ? in_f2[i-1] : in_f2[i]);
 end //end of the for loop inside the generate block
endgenerate

assign out_f3[0] = ((in_f0 && in_f1[2] && in_f2[3]) ? in_f3[4] : in_f3[0]);
generate
 for(i=1; i<=4; i=i+1) begin : f3_loop
  assign out_f3[i] = ((in_f0 && in_f1[2] && in_f2[3]) ? in_f3[i-1] : in_f3[i]);
 end //end of the for loop inside the generate block
endgenerate


endmodule