/* Example 8: by karttu, Dec 12 2004.
              Show the successive Fibonacci numbers when
              the user presses the rightmost push button.

              Version "qs" May 29 2005: queue the successive
              Fibonacci-numbers to the FIFO implemented with ISSI SRAM.
 */

module esim8qs(input CLK,
               input RST,
               input PB_IN,
               input PB_OUT,
               input [1:0] SW_IN,
               output [7:0] SEG_OUT,
               output [3:0] DIGIT_OUT,

               output [17:0] ISSI_ADDR,
               inout [15:0] ISSI_DATA_IO,
               output ISSI_CE1N,
               output ISSI_OEN,
               output ISSI_WEN,
               output ISSI_LB1N,
               output ISSI_UB1N
              );


reg [15:0] f_even = 0;
reg [15:0] f_odd  = 1;

reg odd_one = 0;

reg [17:0] addr_in  = 18'b000000000000000000;
reg [17:0] addr_out = 18'b000000000000000000;

reg  [15:0] num_shown = 0;
wire [15:0] num_out;




wire PBD_IN;  // State of the debounced IN push button.
wire PBD_OUT; // State of the debounced OUT push button.
reg pbd_in_prev = 0; // is saved here also.
reg pbd_out_prev = 0; // is saved here also.

reg [1:0] sw_prev = 0;

debounced_button DBB1(CLK,PB_IN,PBD_IN);
debounced_button DBB2(CLK,PB_OUT,PBD_OUT);

shw16dec DECDISPLAY(CLK,(PBD_IN|PBD_OUT|(sw_prev!=SW_IN)),
                        (SW_IN[0] ? num_shown[15:0]
                                  : (SW_IN[1] ? addr_out[15:0]
                                              : addr_in[15:0])),
                        SEG_OUT,DIGIT_OUT);


wire we = (PBD_IN & ~pbd_in_prev);

issia FIFO(.CLK(CLK),
           .ISSI_ADDR(ISSI_ADDR),
           .ISSI_DATA_IO(ISSI_DATA_IO),
           .ISSI_CE1N(ISSI_CE1N),
           .ISSI_OEN(ISSI_OEN),
           .ISSI_WEN(ISSI_WEN),
           .ISSI_LB1N(ISSI_LB1N),
           .ISSI_UB1N(ISSI_UB1N),
           .STARTWRITE(we),
           .ADDR(we ? addr_in : addr_out),
           .DATAWRITTEN(odd_one ? f_odd : f_even),
           .DATAREAD(num_out),
           .WRITEREADY(writeready)
          );



always @(posedge CLK)
  begin
   if(RST)
    begin
      f_even   <= 0;
      f_odd    <= 1;
      odd_one  <= 0;
      addr_in  <= 0;
      addr_out <= 0;
      pbd_in_prev  <= 0;
      pbd_out_prev <= 0;
      num_shown <= 0;
    end
   else
    begin
     pbd_in_prev  <= PBD_IN;
     pbd_out_prev <= PBD_OUT;
     sw_prev <= SW_IN;

     if(PBD_IN & ~pbd_in_prev) // Only on @(posedge PBD_IN)
      begin
       if(odd_one) f_even <= f_even + f_odd;
       else        f_odd  <= f_even + f_odd;
       odd_one   <= ~odd_one;
       addr_in   <= addr_in+1;
      end

     if(PBD_OUT & ~pbd_out_prev) // Only on @(posedge PBD_OUT)
      begin
       num_shown <= num_out;
       addr_out  <= addr_out+1;
      end

    end
  end

endmodule