/* Example 8: by karttu, Dec 12 2004.
              Show the successive Fibonacci numbers when
              the user presses the rightmost push button.

              Version "q": queue the successive Fibonacci-numbers
              to the FIFO. The motive is to test BRAMs.
 */

module esim8q(CLK,RST,PB_IN,PB_OUT,SW_IN,SEG_OUT,DIGIT_OUT);
input CLK;
input RST;
input PB_IN;
input PB_OUT;
input [1:0] SW_IN;
output [7:0] SEG_OUT;
output [3:0] DIGIT_OUT;


reg [31:0] f_even = 0;
reg [31:0] f_odd  = 1;

reg odd_one = 0;

reg [8:0] addr_in  = 9'b000000000;
reg [8:0] addr_out = 9'b000000000;

reg  [31:0] num_shown = 0;
wire [31:0] num_out;

wire  [3:0] nc4a;
wire  [3:0] nc4b;
wire [31:0] nc32;


wire          low = 1'b0;
wire  [3:0]  low4 = 4'b0000;
wire [31:0] low32 = 32'h00000000;

wire         high = 1'b1;


wire PBD_IN;  // State of the debounced IN push button.
wire PBD_OUT; // State of the debounced OUT push button.
reg pbd_in_prev = 0; // is saved here also.
reg pbd_out_prev = 0; // is saved here also.

reg [1:0] sw_prev = 0;

debounced_button DBB1(CLK,PB_IN,PBD_IN);
debounced_button DBB2(CLK,PB_OUT,PBD_OUT);

shw16dec DECDISPLAY(CLK,(PBD_IN|PBD_OUT|(sw_prev!=SW_IN)),
                        (SW_IN[0] ? num_out[15:0] // num_shown[15:0]
                                  : (SW_IN[1] ? {7'b0,addr_out}
                                              : {7'b0,addr_in})),
                        SEG_OUT,DIGIT_OUT);


wire we = (PBD_IN & ~pbd_in_prev);

RAMB16_S36_S36 fifo(.DOA(nc32), // not connected
                    .DOB(num_out),
                    .DOPA(nc4a), // not connected
                    .DOPB(nc4b), // not connected
                    .ADDRA(addr_in),
                    .ADDRB(addr_out),
                    .CLKA(CLK),
                    .CLKB(CLK),
                    .DIA(odd_one ? f_odd : f_even),
                    .DIB(low32),
                    .DIPA(low4),
                    .DIPB(low4),
                    .ENA(RST | we),
                    .ENB(high),
                    .SSRA(RST),
                    .SSRB(RST),
                    .WEA(we),
                    .WEB(low)
                   );

always @(posedge CLK)
  begin
   if(RST)
    begin
      f_even   <= 0;
      f_odd    <= 1;
      odd_one  <= 0;
      addr_in  <= 0;
      addr_out <= 0;
      pbd_in_prev  <= 0;
      pbd_out_prev <= 0;
      num_shown <= 0;
    end
   else
    begin
     pbd_in_prev  <= PBD_IN;
     pbd_out_prev <= PBD_OUT;
     sw_prev <= SW_IN;

     if(PBD_IN & ~pbd_in_prev) // Only on @(posedge PBD_IN)
      begin
       if(odd_one) f_even <= f_even + f_odd;
       else        f_odd  <= f_even + f_odd;
       odd_one <= ~odd_one;
       addr_in <= addr_in+1;
      end

     if(PBD_OUT & ~pbd_out_prev) // Only on @(posedge PBD_OUT)
      begin
       num_shown <= num_out;
       addr_out <= addr_out+1;
      end

    end
  end

endmodule