JDF G
// Created by Project Navigator ver 1.0
PROJECT esim8bb
DESIGN esim8bb
DEVFAM spartan3
DEVFAMTIME 0
DEVICE xc3s200
DEVICETIME 0
DEVPKG ft256
DEVPKGTIME 0
DEVSPEED -4
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
SOURCE esim8bb.v
SOURCE debounce.v
SOURCE shw16decbb.v
SOURCE div16by10.v
DEPASSOC esim8bb esim8bb.ucf
[STATUS-ALL]
esim8bb.ngcFile=WARNINGS,1104453839
[STRATEGY-LIST]
Normal=True