`timescale 1 ns / 1 ns

module esim6_esim6tb_v_tf();

// DATE:     00:41:45 11/22/2004 
// MODULE:   esim6
// DESIGN:   esim6
// FILENAME: esim6tb.v
// PROJECT:  esim6
// VERSION:  


// Inputs
    reg CLK;
    reg [7:0] SW_IN;


// Outputs
    wire [7:0] SEG_OUT;
    wire [3:0] DIGIT_OUT;


// Bidirs


// Instantiate the UUT
    esim6 uut (
        .CLK(CLK), 
        .SW_IN(SW_IN), 
        .SEG_OUT(SEG_OUT), 
        .DIGIT_OUT(DIGIT_OUT)
        );


// Initialize Inputs
    `ifdef auto_init

        initial begin
            CLK = 0;
            SW_IN = 0;
        end

    `endif

// ////////////////
// Create the clock
// (And initialize the switches)
// Note that F3 = 243 in decimal,
// so the following 7-seg masks
// should be generated:
// 10110000 (for 3)
// 10011001 (for 4)
// 10100100 (for 2)
// 11000000 (for 0)
// DIGIT_OUT should toggle 1110, 1101, 1011, 0111.
// ////////////////

  integer cycles = 0;

  initial begin
    SW_IN = 8'b11110011;
    CLK = 0;
    forever #8
     begin
      CLK = ~CLK;
      if(CLK) cycles = cycles + 1;
     end
  end

endmodule