/* Example 6: by karttu, Nov 23 2004.
              Show the binary number specified in the slide switches 0-7
              in the four 7-segment digits, in zero-prepended DECIMAL.
              This is the first cut, and the logic is not very nice!
 */

module esim6(CLK,SW_IN,SEG_OUT,DIGIT_OUT);
input CLK;
input [7:0] SW_IN;
output [7:0] SEG_OUT;
output [3:0] DIGIT_OUT;

function [6:0] HEX2LED;
  input [3:0] HEX;

  begin
     case (HEX)
	4'b0001 : HEX2LED = 7'b1111001;	//1
	4'b0010 : HEX2LED = 7'b0100100;	//2
	4'b0011 : HEX2LED = 7'b0110000;	//3
	4'b0100 : HEX2LED = 7'b0011001;	//4
	4'b0101 : HEX2LED = 7'b0010010;	//5
	4'b0110 : HEX2LED = 7'b0000010;	//6
	4'b0111 : HEX2LED = 7'b1111000;	//7
	4'b1000 : HEX2LED = 7'b0000000;	//8
	4'b1001 : HEX2LED = 7'b0010000;	//9
	4'b1010 : HEX2LED = 7'b0001000;	//A
	4'b1011 : HEX2LED = 7'b0000011;	//b
	4'b1100 : HEX2LED = 7'b1000110;	//C
	4'b1101 : HEX2LED = 7'b0100001;	//d
	4'b1110 : HEX2LED = 7'b0000110;	//E
	4'b1111 : HEX2LED = 7'b0001110;	//F
	default : HEX2LED = 7'b1000000;	//0
     endcase
  end
endfunction

`define NUM {8'b0,SW_IN}
reg [15:0] n = 0;
reg [3:0] digit  = 0;
wire [15:0] new_n;
wire [3:0] digout;

wire division_ready;
reg restart_div = 0;

parameter msb = 15;
reg [msb:0] delay_counter = 0;
wire [1:0] d = delay_counter[msb:(msb-1)]; // Two most significant bits.

assign SEG_OUT[6:0] = HEX2LED(digit);
assign SEG_OUT[7] = 1'b1; // Don't light the dp.
assign DIGIT_OUT = ((2'b00 == d) ? 4'b1110
                                 : (2'b01 == d) ? 4'b1101
                                 : (2'b10 == d) ? 4'b1011
                                 : 4'b0111); // I.e. (2'b11 == d)

div16by10 DIGITGENERATOR(CLK,restart_div,n,new_n,digout,division_ready);

always @(posedge CLK)
  begin
    delay_counter <= delay_counter+1; // Wraps around, eventually.
    if(~|(delay_counter[msb-2:0])) // Just incremented to the next state?
     begin
       if(2'b00 == d) n <= `NUM; // Initialize n for the rightmost digit.
       restart_div <= 1; // Make sure the divider is ready to start.
     end
    else if((delay_counter[msb-2:0]) < 19) // Time to divide?
     begin
       restart_div <= 0; // The divider is free to run on cycles 1-18.
     end
    else
     begin                // For most of the time keep the divider in
       restart_div <= 1;  // perpetual restart state.
     end

    if(division_ready) // About sixteen cycles after letting it loose.
     begin
       digit <= digout; // Save the remainder while it is still valid.
       n <= new_n;      // Ditto for the quotient.
     end
  end

endmodule