`timescale 1 ns / 1 ns

module esim5_esim5tb_v_tf();

// DATE:     00:41:45 11/22/2004 
// MODULE:   esim5
// DESIGN:   esim5
// FILENAME: esim5tb.v
// PROJECT:  esim5
// VERSION:  


// Inputs
    reg CLK;
    reg [7:0] SW_IN;


// Outputs
    wire [7:0] SEG_OUT;
    wire [3:0] DIGIT_OUT;


// Bidirs


// Instantiate the UUT
    esim5 uut (
        .CLK(CLK), 
        .SW_IN(SW_IN), 
        .SEG_OUT(SEG_OUT), 
        .DIGIT_OUT(DIGIT_OUT)
        );


// Initialize Inputs
    `ifdef auto_init

        initial begin
            CLK = 0;
            SW_IN = 0;
        end

    `endif

// ////////////////
// Create the clock
// (And initialize the switches)
// Note that the lower nybble (0001)
// generates 1's 7-segment mask 01111001
// to SEG_OUT, and the higher nybble (1111)
// generates F's 7-segment mask 10001110
// to SEG_OUT.
// DIGIT_OUT should toggle between 1110 and 1101.
// ////////////////
  initial begin
    SW_IN = 8'b11110001;
    CLK = 0;
    forever #20 CLK = ~CLK;
  end

endmodule