/* Example 4: "swbinto2segs"
              Show the binary number specified in the slide switches 0-7
              in the two righmost digits, in hexadecimal.

   This simple-minded design works in practice only
   if the clock is set to a SLOW frequency like 0.5MHz (2000 ns),
   as the combinational delays involved are of the order ~ 10 ns.
   (Note the difference between ModelSim "Simulate Behavioral Model"
   and "Simulate Post-Place & Route Verilog Model".)
 */

module esim4(CLK,SW_IN,SEG_OUT,DIGIT_OUT);
input CLK;
input [7:0] SW_IN;
output [7:0] SEG_OUT;
output [3:0] DIGIT_OUT;

function [6:0] HEX2LED;
  input [3:0] HEX;

  begin
     case (HEX)
	4'b0001 : HEX2LED = 7'b1111001;	//1
	4'b0010 : HEX2LED = 7'b0100100;	//2
	4'b0011 : HEX2LED = 7'b0110000;	//3
	4'b0100 : HEX2LED = 7'b0011001;	//4
	4'b0101 : HEX2LED = 7'b0010010;	//5
	4'b0110 : HEX2LED = 7'b0000010;	//6
	4'b0111 : HEX2LED = 7'b1111000;	//7
	4'b1000 : HEX2LED = 7'b0000000;	//8
	4'b1001 : HEX2LED = 7'b0010000;	//9
	4'b1010 : HEX2LED = 7'b0001000;	//A
	4'b1011 : HEX2LED = 7'b0000011;	//b
	4'b1100 : HEX2LED = 7'b1000110;	//C
	4'b1101 : HEX2LED = 7'b0100001;	//d
	4'b1110 : HEX2LED = 7'b0000110;	//E
	4'b1111 : HEX2LED = 7'b0001110;	//F
	default : HEX2LED = 7'b1000000;	//0
     endcase
  end
endfunction

reg hi_nybble_now = 0;

assign SEG_OUT[6:0] = HEX2LED(hi_nybble_now ? SW_IN[7:4] : SW_IN[3:0]);
assign SEG_OUT[7] = hi_nybble_now; // For debugging, keep the 2nd dp off.
assign DIGIT_OUT = ((0 == hi_nybble_now) ? 4'b1110 : 4'b1101);

always @(posedge CLK)
  begin
    hi_nybble_now <= ~hi_nybble_now;
  end

endmodule