JDF G
// Created by Project Navigator ver 1.0
PROJECT esim12b
DESIGN esim12b
DEVFAM spartan3
DEVFAMTIME 0
DEVICE xc3s200
DEVICETIME 0
DEVPKG ft256
DEVPKGTIME 0
DEVSPEED -4
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
SOURCE esim12b.v
SOURCE debounce.v
SOURCE inc4fexb.v
SOURCE show4hex.v
DEPASSOC esim12b esim12b.ucf
[STRATEGY-LIST]
Normal=True