`timescale 1 ns / 1 ns

module div16by10_div16by10tb_v_tf();

// DATE:     17:59:34 11/23/2004 
// MODULE:   div16by10
// DESIGN:   div16by10
// FILENAME: div16by10tb.v
// PROJECT:  div16by10
// VERSION:  

    integer test_counter;

// Inputs
    reg clk;
    reg start;
    reg [15:0] dividend;


// Outputs
    wire [15:0] quotient;
    wire [3:0] remainder;
    wire ready;


// Bidirs


// Instantiate the UUT
    div16by10 uut (
        .clk(clk), 
        .start(start), 
        .dividend(dividend), 
        .quotient(quotient), 
        .remainder(remainder), 
        .ready(ready)
        );


// Initialize Inputs
    `ifdef auto_init

        initial begin
            clk = 0;
            start = 0;
            dividend = 0;
        end

    `endif


// ////////////////
// Create the clock
// and increment the dividend
// every 20th cycle, starting from
// value 0.
// When start goes 1, clk should go
// 1 as well, so that this simulation
// would work at all.
// ////////////////
  initial begin
    dividend = 32766;
    clk = 0;
    start = 0;
    test_counter = 15; // After three cycles we are ready to start.
    forever #10
     begin
      clk = ~clk;
      start = !test_counter;
      if(!clk)
       begin
         test_counter = test_counter + 1;
         if(20 == test_counter)
          begin
            test_counter = 0;
            dividend = dividend+1;
            start = 1;
          end
         else
          begin
            start = 0;
          end
       end
     end
  end

endmodule