JDF G
// Created by Project Navigator ver 1.0
PROJECT div16by10
DESIGN div16by10
DEVFAM spartan3
DEVFAMTIME 0
DEVICE xc3s200
DEVICETIME 0
DEVPKG ft256
DEVPKGTIME 0
DEVSPEED -4
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
SOURCE div16by10.v
STIMULUS div16by10tb.v
[STATUS-ALL]
div16by10.ngcFile=WARNINGS,1101230036
[STRATEGY-LIST]
Normal=True